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Disambiguation of "Pravadelli, Graziano"

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An error simulation based approach to measure error coverage of formal properties.

, , , , , and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2002)

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Graziano Pinna

Thomas Kadner Graziano

 

Other publications of authors with the same name

Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions., , and . IEEE Trans. Computers, 60 (12): 1730-1743 (2011)Model-driven design and validation of embedded software., , , , , , and . AST, page 98-104. ACM, (2011)An error simulation based approach to measure error coverage of formal properties., , , , , and . ACM Great Lakes Symposium on VLSI, page 53-58. ACM, (2002)Vacuity analysis for property qualification by mutation of checkers., , and . DATE, page 478-483. IEEE Computer Society, (2010)Reusing RTL Assertion Checkers for Verification of SystemC TLM Models., , , , , , , , and . J. Electron. Test., 31 (2): 167-180 (2015)On the integration of model-driven design and dynamic assertion-based verification for embedded software., , , , , , and . J. Syst. Softw., 86 (8): 2013-2033 (2013)A model-based design flow for Dynamic Partial Reconfigurable FPGAs., , and . SMC, page 3099-3103. IEEE, (2019)Fostering Human Activity Recognition Workflows: An Open-Source Baseline Framework., , and . ICDH, page 75-80. IEEE, (2023)From Informal Specifications to an ABV Framework for Industrial Firmware Verification., , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 179-204. Springer, (2020)Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions., and . VLSI-SoC, page 1-6. IEEE, (2022)