( en | de | ru )

 

Disambiguation of "Shalash, Ahmed"

Author of the publication

copydeleteadd this publication to your clipboard
A proposed methodology for designing reconfigurable solutions.

, , , , and . IDT, page 53-58. IEEE, (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mohamed Salah Shalash

Ahmed Fattah Ahmed Ahmed

Ejaz Ahmed

Yasar Luqman Ahmed

Sayed Tawfik Ahmed

 

Other publications of authors with the same name

A reconfigurable hardware platform implementation for software defined radio using dynamic partial reconfiguration on Xilinx Zynq FPGA., , , , , , , , , and . MWSCAS, page 1540-1543. IEEE, (2017)Memory conflict analysis for a multi-standard, reconfigurable turbo decoder., , , and . ISCAS, page 2701-2704. IEEE, (2011)A reconfigurable baseband processor for wireless OFDM synchronization sub-system., , and . ISCAS, page 2385-2388. IEEE, (2011)All digital time tracking loop for DVB-H and DVB-T., and . ISCAS, page 458-461. IEEE, (2011)Throughput maximizing FIR filterbank for MIMO LTI wireline channels., and . ICC, page 16-20. IEEE, (2004)Theoretical and practical limits of next-generation high-speed digital subscriber loops., and . IEEE Trans. Commun., 48 (9): 1447-1450 (2000)Low complexity maximum likelihood estimation of time and frequency offset for DVB-T2., , and . NEWCAS, page 1-4. IEEE, (2013)FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine., , and . ISCAS, page 1255-1258. IEEE, (2011)Multiple access over wireline channels using orthogonal signaling., and . ISCAS (4), page 580-583. IEEE, (1999)Low complexity timing synchronization and channel estimation for DVB-T2 over long echo channels., , and . Sarnoff Symposium, page 29-33. IEEE, (2015)