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A second-order switched-capacitor ΔΣ modulator using very incomplete settling., , and . ISCAS, page 1367-1370. IEEE, (2011)Design methodology for Sigma-Delta modulators based on a genetic algorithm using hybrid cost functions., , , and . ISCAS, page 301-304. IEEE, (2012)Design of Improved Rail-to-Rail Low-Distortion and Low-Stress Switches in Advanced CMOS Technologies., , and . ICECS, page 218-221. IEEE, (2007)Design of Robust CMOS Amplifiers Combining Advanced Low-Voltage and Feedback Techniques., , , , and . DoCEIS, volume 372 of IFIP Advances in Information and Communication Technology, page 421-428. Springer, (2012)Fully integrated and reconfigurable architecture for coherent self-testing of IQ ADCs., , , and . ISCAS, page 1927-1930. IEEE, (2010)An improved low-voltage low-power CMOS comparator to be used in high-speed pipeline ADCs., , , and . ISCAS (5), page 141-144. IEEE, (2002)A Switched-Capacitor Band-Pass Biquad Filter Using a Simple Quasi-unity Gain Amplifier., , and . DoCEIS, volume 394 of IFIP Advances in Information and Communication Technology, page 582-589. Springer, (2013)A Systematic Design Methodology for Optimization of Sigma-Delta Modulators Based on an Evolutionary Algorithm., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (9): 3544-3556 (2019)A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 67-II (2): 230-234 (2020)15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM., , and . ISSCC, page 274-275. IEEE, (2016)