Author of the publication

Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture.

, , , , , , , and . Proc. VLDB Endow., 14 (11): 2087-2100 (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices., , , and . SLIP@DAC, page 1:1-1:8. ACM, (2018)Optimality study of resource binding with multi-Vdds., , , and . DAC, page 580-585. ACM, (2006)Throughput-oriented kernel porting onto FPGAs., , , , and . DAC, page 11:1-11:10. ACM, (2013)C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs., , and . DAC, page 205:1-205:6. ACM, (2014)High-level synthesis with behavioral level multi-cycle path analysis., , , , and . FPL, page 1-8. IEEE, (2013)A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation., , , , , and . DATE, page 1789-1794. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling., , and . ASP-DAC, page 761-768. IEEE, (2016)Fast large-scale optimal power flow analysis for smart grid through network reduction., and . ASP-DAC, page 373-378. IEEE, (2014)Behavioral-level IP integration in high-level synthesis., , , and . FPT, page 172-175. IEEE, (2015)Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 650-663 (2016)