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A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation.

, , , , and . IEEE J. Solid State Circuits, 33 (11): 1741-1751 (1998)

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A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 34 (5): 645-652 (1999)A portable digital DLL for high-speed CMOS interface circuits., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 34 (5): 632-644 (1999)Metastability in CMOS library elements in reduced supply and technology scaled applications., and . IEEE J. Solid State Circuits, 30 (1): 39-46 (January 1995)A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation., , , , and . IEEE J. Solid State Circuits, 33 (11): 1741-1751 (1998)Optimization of phase-locked loop circuits via geometric programming., , , , , , , and . CICC, page 377-380. IEEE, (2003)Power-efficient metastability error reduction in CMOS flash A/D converters., and . IEEE J. Solid State Circuits, 31 (8): 1132-1140 (1996)Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver., , , , , , , , , and 10 other author(s). ISSCC, page 350-351. IEEE, (2011)