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VeriCDF: a new verification methodology for charged device failures., , and . DAC, page 874-879. ACM, (2002)Minimum delay optimization for domino circuits - a coupling-aware approach., , , and . ACM Trans. Design Autom. Electr. Syst., 8 (2): 202-213 (2003)Coupling-aware high-level interconnect synthesis IC layout., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (1): 157-164 (2004)Energy-efficient skewed static logic with dual Vt: design and synthesis., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 64-70 (2003)Noise constrained power optimization for dual VT domino logic., , and . ISCAS (4), page 158-161. IEEE, (2001)Energy-efficient skewed static logic design with dual Vt., , and . ISCAS (4), page 882-885. IEEE, (2001)Noise-aware interconnect power optimization in domino logic synthesis., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (1): 79-89 (2003)ScienceIoT: Evolution of the Wireless Infrastructure of KREONET., , , , , , and . Sensors, 21 (17): 5852 (2021)Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain., , and . DATE, page 260-265. IEEE Computer Society, (2002)Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design., , , , and . ICCAD, page 318-321. IEEE Computer Society, (2000)