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DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment., , , , , and . ISPD, page 91-98. ACM, (2017)Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection., , , , , , and . CoRR, (2018)High performance dummy fill insertion with coupling and uniformity constraints., , and . DAC, page 71:1-71:6. ACM, (2015)Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (5): 1448-1452 (2022)AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4139-4151 (November 2023)CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (12): 5034-5047 (December 2023)Adaptive Layout Decomposition With Graph Embedding Neural Networks., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 5030-5042 (2022)FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2317-2330 (July 2023)GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (2): 373-385 (2021)Interactive Analog Layout Editing With Instant Placement and Routing Legalization., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (3): 698-711 (March 2023)