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AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection., , , and . DAC, page 795-800. ACM, (2011)High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths., , , and . DAC, page 161:1-161:6. ACM, (2015)ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction., , , and . DAC, page 504-509. ACM, (2008)Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis., , , , and . DAC, page 148-153. IEEE, (2007)PASAP: power aware structured ASIC placement., and . ISLPED, page 395-400. ACM, (2010)On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes., , , , and . IEEE Trans. Inf. Forensics Secur., 14 (2): 347-359 (2019)Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (9): 1613-1626 (2018)Light in AI: Toward Efficient Neurocomputing With Optical Neural Networks - A Tutorial., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (6): 2581-2585 (2022)PiPSim: A Behavior-Level Modeling Tool for CNN Processing-in-Pixel Accelerators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (1): 141-150 (January 2024)Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (6): 905-917 (2013)