( en | de | ru )

 

Disambiguation of "Wong, Martin D. F."

Author of the publication

copydeleteadd this publication to your clipboard
On simulated annealing in EDA.

. ISPD, page 63-64. ACM, (2012)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Alexander D F Lahmann

Blaise F D Bourgeois

Walter Wong

Martin F Almstetter

Martin F Polaschek

 

Other publications of authors with the same name

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation., , , and . VLSI Design, 15 (3): 587-594 (2002)Channel/switchbox definition for VLSI building-block layout., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (12): 1485-1493 (1991)A new approach to three- or four-layer channel routing., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 7 (10): 1094-1104 (1988)A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2784-2794 (2006)Timing-driven routing for FPGAs based on Lagrangian relaxation., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 506-510 (2003)Performance-driven channel pin assignment algorithms., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (7): 849-857 (1995)Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (7): 1256-1269 (2007)Matching-based algorithm for FPGA channel segmentation design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (6): 784-791 (2001)NP-Completeness and an Approximation Algorithm for Rectangle Escape Problem With Application to PCB Routing., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (9): 1356-1365 (2012)Floorplan Design for Multimillion Gate FPGAs., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2795-2805 (2006)