From post

Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences.

, и . VLSI Design, стр. 335-340. IEEE Computer Society, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем