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Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms.

, , , , and . IEEE Trans. Computers, 65 (2): 562-576 (2016)

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HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs., , , and . FPGA, page 222-231. ACM, (2019)Global Real-Time Memory-Centric Scheduling for Multicore Systems., , , , and . IEEE Trans. Computers, 65 (9): 2739-2751 (2016)Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems., and . IEEE Trans. Computers, 59 (3): 400-415 (2010)A composable worst case latency analysis for multi-rank DRAM devices under open row policy., , and . Real Time Syst., 52 (6): 761-807 (2016)Real-Time Computing on Multicore Processors., , , , , , , , , and 1 other author(s). Computer, 49 (9): 69-77 (2016)A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources., , , , and . ECRTS, volume 262 of LIPIcs, page 17:1-17:25. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)A Requests Bundling DRAM Controller for Mixed-Criticality Systems., and . RTAS, page 247-258. IEEE Computer Society, (2017)Memory Servers for Multicore Systems., and . RTAS, page 97-108. IEEE Computer Society, (2016)A Slot-Based Real-Time Scheduling Algorithm for Concurrent Transactions in NoC., , and . RTCSA (1), page 329-338. IEEE Computer Society, (2011)A design-space exploration for allocating security tasks in multicore real-time systems., , , and . DATE, page 225-230. IEEE, (2018)