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Virtual-machine-based emulation of future generation high-performance computing systems.

, , , , , , , and . Int. J. High Perform. Comput. Appl., 26 (2): 125-135 (2012)

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Process variation characterization of chip-level multiprocessors., , , , and . DAC, page 694-697. ACM, (2009)Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging., , and . CODES+ISSS, page 235-244. ACM, (2012)Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems., , and . CODES+ISSS, page 105-110. ACM, (2007)Exploring circuit timing-aware language and compilation., , and . ASPLOS, page 345-356. ACM, (2011)Exploration of associative power management with instruction governed operation for ultra-low power design., , , and . DAC, page 152:1-152:6. ACM, (2016)Enabling Deep Voltage Scaling in Delay Sensitive L1 Caches., and . DSN, page 192-202. IEEE Computer Society, (2016)Run-time power estimation in high performance microprocessors., and . ISLPED, page 135-140. ACM, (2001)Process variation aware cache leakage management., and . ISLPED, page 262-267. ACM, (2006)Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors., , , and . IEEE Micro, 27 (3): 49-62 (2007)Reliability Modeling and Management of Nanophotonic On-Chip Networks., , , , , , , , , and 1 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 98-111 (2012)