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pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator.

J. Poulton, J. Wilson, W. Turner, B. Zimmer, X. Chen, S. Kudva, S. Song, S. Tell, N. Nedovic, W. Zhao, S. Sudhakaran, C. Gray, and W. Dally. IEEE J. Solid State Circuits, 54 (1): 43-54 (2019)

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H J M Turner

Ernst Turner

John Turner

Anke Turner

Ernst Turner

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A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.S. Song, J. Poulton, X. Chen, B. Zimmer, S. Tell, W. Turner, S. Kudva, N. Nedovic, J. Wilson, C. Gray and 1 other author(s). CICC, page 1-4. IEEE, (2019)A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS.Y. Nishi, J. Poulton, W. Turner, X. Chen, S. Song, B. Zimmer, S. Tell, N. Nedovic, J. Wilson, W. Dally and 1 other author(s). IEEE J. Solid State Circuits, 58 (4): 1062-1073 (2023)A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS.Y. Nishi, J. Poulton, X. Chen, S. Song, B. Zimmer, W. Turner, S. Tell, N. Nedovic, J. Wilson, W. Dally and 1 other author(s). VLSI Technology and Circuits, page 154-155. IEEE, (2022)A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.Y. Nishi, J. Poulton, W. Turner, X. Chen, S. Song, B. Zimmer, S. Tell, N. Nedovic, J. Wilson, W. Dally and 1 other author(s). IEEE J. Solid State Circuits, 59 (4): 1146-1157 (April 2024)6.6 Reference-Noise Compensation Scheme for Single-Ended Package-to-Package Links.X. Chen, N. Nedovic, S. Tell, S. Kudva, B. Zimmer, T. Greer, J. Poulton, S. Song, W. Turner, J. Wilson and 1 other author(s). ISSCC, page 126-128. IEEE, (2020)Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.M. Liu, W. Turner, G. Kokai, B. Khailany, D. Pan, and H. Ren. DATE, page 1372-1377. IEEE, (2021)A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS.Y. Nishi, J. Poulton, X. Chen, S. Song, B. Zimmer, W. Turner, S. Tell, N. Nedovic, J. Wilson, W. Dally and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)TAG: Learning Circuit Spatial Embedding from Layouts.K. Zhu, H. Chen, W. Turner, G. Kokai, P. Wei, D. Pan, and H. Ren. ICCAD, page 66:1-66:9. ACM, (2022)A 4.7 T/11.1 T NMR Compliant 50 nW Wirelessly Programmable Implant for Bioartificial Pancreas In Vivo Monitoring.W. Turner, and R. Bashirullah. IEEE J. Solid State Circuits, 51 (2): 473-483 (2016)ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks.H. Ren, G. Kokai, W. Turner, and T. Ku. DAC, page 1-6. IEEE, (2020)

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Disambiguation of "Turner, Walker J."

Please choose a person to relate this publication to

H J M Turner

Ernst Turner

John Turner

Anke Turner

Ernst Turner

Other publications of authors with the same name

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