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Disambiguation of "Tell, Stephen G."

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A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.

, , , , , , , , , , and . CICC, page 1-4. IEEE, (2019)

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Stephen G Hickey

Anna Tell

Ilse Tell

Gabriele Tell

Rolf Tell

 

Other publications of authors with the same name

A programmable network interface for a message-based multicomputer., , and . Comput. Commun. Rev., 24 (3): 8-17 (1994)Simba: scaling deep-learning inference with chiplet-based architecture., , , , , , , , , and 7 other author(s). Commun. ACM, 64 (6): 107-116 (2021)A 77 MHz Relaxation Oscillator in 5nm FinFET with 3ns TIE over 10K cycles and ±0.3% Thermal Stability using Frequency-Error Feedback Loop., , , , , and . A-SSCC, page 1-3. IEEE, (2021)Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture., , , , , , , , , and 7 other author(s). MICRO, page 14-27. ACM, (2019)A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications., , , , , , and . ISSCC, page 404-405. IEEE, (2013)An Engineering Environment for Hardware/Software Co-Simulation., , and . DAC, page 129-134. IEEE Computer Society Press, (1992)A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 54 (1): 43-54 (2019)A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm., , , , , , , , and . IEEE J. Solid State Circuits, 58 (4): 1129-1141 (2023)An On-Chip Relaxation Oscillator in 5-nm FinFET Using a Frequency-Error Feedback Loop., , , , , and . IEEE J. Solid State Circuits, 57 (10): 2898-2908 (2022)BioSCAN: a network sharable computational resource for searching biosequence databases., , , and . Comput. Appl. Biosci., 12 (3): 191-196 (1996)