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A 3.8 mW/Gbps Quad-Channel 8.5-13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 51 (4): 881-892 (2016)Design of a 100+ meter 12Gb/s/Lane Copper Cable Link Based on Clock-Forwarding.. University of California, Los Angeles, USA, (2012)base-search.net (ftcdlib:qt587266mn).56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology., , , , , and . CICC, page 1-6. IEEE, (2021)6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology., , , , , , , , , and 8 other author(s). ISSCC, page 118-120. IEEE, (2020)29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 484-485. IEEE, (2017)A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding., , , , , and . VLSIC, page 108-109. IEEE, (2012)Clocking Links in Multi-chip Packages: A Case Study., , , , , , and . Hot Interconnects, page 96-103. IEEE Computer Society, (2010)A 100+ Meter 12 Gb/s/Lane Copper Cable Link Based on Clock-Forwarding., , , and . IEEE J. Solid State Circuits, 48 (4): 1085-1098 (2013)A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET., , , , , , , , , and 11 other author(s). ISSCC, page 110-111. IEEE, (2023)A 3.8 mW/Gbps quad-channel 8.5-13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS., , , , , , , , , and 3 other author(s). VLSIC, page 348-. IEEE, (2015)