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Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.

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Delay Test with Embedded Test Pattern Generator., and . J. Inf. Sci. Eng., 29 (3): 545-556 (2013)Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (11): 2586-2594 (2006)Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture., , , and . ATS, page 95-100. IEEE, (2007)TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning., , , , , , , and . ITC, page 1-6. IEEE, (2019)De Bruijn graph-based communication modeling for fault tolerance in smart grids., , and . APCCAS, page 623-626. IEEE, (2012)Design and Synthesis of Self-Checking VLSI Circuits and Systems., and . ICCD, page 578-581. IEEE Computer Society, (1991)PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques., , , , , , and . ETS, page 1-6. IEEE, (2020)Leakage Monitoring Technique in Near-Threshold Systems with a Time-Based Bootstrapped Ring Oscillator., , and . Asian Test Symposium, page 91-96. IEEE Computer Society, (2013)Test generation for combinational hardware Trojans., , , and . AsianHOST, page 1-6. IEEE Computer Society, (2016)Fast and accurate statistical static timing analysis., , and . ISCAS, page 2555-2558. IEEE, (2014)