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Disambiguation of "Yamaji, Takafumi"

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1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters.

, , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (2): 454-460 (2008)

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Other publications of authors with the same name

55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers., , , , and . IEEE J. Solid State Circuits, 41 (7): 1589-1595 (2006)A four-input beam-forming downconverter for adaptive antennas., , , , and . IEEE J. Solid State Circuits, 38 (10): 1619-1625 (2003)1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (2): 454-460 (2008)55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers., , , , and . ESSCIRC, page 527-530. IEEE, (2005)A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop., , and . ISSCC, page 98-100. IEEE, (2011)A 2-GHz Down-Converter with 3-dB Bandwidth of 600 MHz Using LO Signal Suppressing Output Buffer., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (2): 286-292 (2002)A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching., , , and . IEEE J. Solid State Circuits, 37 (7): 809-816 (2002)Harmonic Signal Rejection Schemes of Polyphase Downconverters., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (10): 2308-2317 (2011)All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (5): 1113-1121 (2013)A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters., , , , and . CICC, page 501-504. IEEE, (2006)