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Invariant Relations for Automata - A Proposal.

, and . Elektronische Informationsverarbeitung und Kybernetik, 16 (4): 147-169 (1980)

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Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten II., and . Elektronische Informationsverarbeitung und Kybernetik, 9 (9): 549-567 (1973)Zur Verarbeitung von Zufallsfolgen durch abstrakte Automaten I., and . Elektronische Informationsverarbeitung und Kybernetik, 9 (7/8): 433-454 (1973)Modified DEC BCH codes for parallel correction of 3-bit errors comprising a pair of adjacent errors., , and . IOLTS, page 116-121. IEEE, (2014)Memories for Parallel Subtree-Access., and . Parallel Algorithms and Architectures, volume 269 of Lecture Notes in Computer Science, page 122-130. Springer, (1987)Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs., and . J. Electron. Test., 4 (3): 267-281 (1993)Self-checking Carry-selectAdder with Sum-bit Duplication., , , and . ARCS Workshops, volume P-41 of LNI, page 84-91. GI, (2004)Test set enrichment using a probabilistic fault model and the theory of output deviations., , and . DATE, page 1270-1275. European Design and Automation Association, Leuven, Belgium, (2006)Parallel matrix multiplication on an array-logical processor., , , and . Recent Issues in Pattern Analysis and Recognition, volume 399 of Lecture Notes in Computer Science, page 72-78. Springer, (1989)New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability., , and . IOLTS, page 37-42. IEEE Computer Society, (2008)Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits., , , and . IOLTS, page 35-. IEEE Computer Society, (2003)