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Disambiguation of "Cho, Soo-In"

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16-Mb synchronous DRAM with 125-Mbyte/s data rate.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 29 (4): 529-533 (April 1994)

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In Soo Gambert

Byoung-Soo Cho

In-Soo Park

In-Sung Cho

In-Soo Kim

 

Other publications of authors with the same name

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control., , , , , , and . IEEE J. Solid State Circuits, 40 (1): 223-232 (2005)A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme., , , , , , , , and . IEEE J. Solid State Circuits, 33 (5): 779-786 (1998)A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 31 (11): 1635-1644 (1996)16-Mb synchronous DRAM with 125-Mbyte/s data rate., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 29 (4): 529-533 (April 1994)A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces., , , , and . IEEE J. Solid State Circuits, 44 (5): 1522-1530 (2009)A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation., , , , and . CICC, page 473-476. IEEE, (2003)A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 34 (5): 645-652 (1999)A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 33 (11): 1703-1710 (1998)A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme., , , , , and . IEEE J. Solid State Circuits, 37 (2): 245-250 (2002)A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor., , , , , , , , and . IEEE J. Solid State Circuits, 38 (4): 631-640 (2003)