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Reduction of diagnostic fail data volume and tester time using a dynamic N-cover algorithm.

, , , , , and . VTS, page 1-6. IEEE Computer Society, (2016)

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Test reordering for improved scan chain diagnosis using an enhanced defect diagnosis procedure., , , and . ITC, page 1-9. IEEE, (2017)Defect diagnosis based on DFM guidelines., , , and . VTS, page 206-211. IEEE Computer Society, (2010)A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction., , and . ATS, page 138-143. IEEE Computer Society, (2016)An Experimental Study of N-Detect Scan ATPG Patterns on a Processor., , , , , and . VTS, page 23-30. IEEE Computer Society, (2004)Theorems for Efficient Identification of Indistinguishable Fault Pairs in Synchronous Sequential Circuits., , and . VTS, page 181-186. IEEE Computer Society, (2002)Using Scan-Dump Values to Improve Functional-Diagnosis Methodology., , , , , and . VTS, page 231-238. IEEE Computer Society, (2007)Innovative practices session 5C: Advancements in test -keeping moore moving!. VTS, page 1. IEEE Computer Society, (2015)Improving Precision Using Mixed-level Fault Diagnosis., , and . ITC, page 1-10. IEEE Computer Society, (2006)Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation., , , , and . VTS, page 351-358. IEEE Computer Society, (2003)Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults., , , and . VLSI Design, page 475-480. IEEE Computer Society, (2004)