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A High-Performance Hardwired CABAC Decoder., and . ICASSP (2), page 37-40. IEEE, (2007)A Memory-Efficient and Highly Parallel Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (6): 866-874 (2010)An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration., and . ACM Trans. Embed. Comput. Syst., 9 (4): 35:1-35:39 (2010)Effective enforcement of path-delay constraints inperformance-driven placement., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (1): 15-22 (2002)A fast transistor-chaining algorithm for CMOS cell layout., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 9 (7): 781-786 (1990)Channel density reduction by routing over the cells., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (8): 1067-1071 (1991)RNNAccel: A Fusion Recurrent Neural Network Accelerator for Edge Intelligence., , , , , and . CoRR, (2020)Integration, Verification and Layout of a Complex Multimedia SOC, , and . CoRR, (2007)A Systolic Algorithm for the k-Nearest Neighbors Problem., , and . IEEE Trans. Computers, 41 (1): 103-108 (1992)A hardware accelerator for context-based adaptive binary arithmetic decoding in H.264/AVC., , and . ISCAS (5), page 4525-4528. IEEE, (2005)