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Disambiguation of "Ramanarayanan, Rajaraman"

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An IA-32 processor with a wide voltage operating range in 32nm CMOS.

, , , , , , , , , , , , , , , , , , and . Hot Chips Symposium, page 1-37. IEEE, (2012)

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Srinivasan Rajaraman

Gnana Oli Rajaraman

 

Other publications of authors with the same name

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors., , , , , , and . VLSI Design, page 251-258. IEEE Computer Society, (2007)A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores., , , , and . VLSI Design, page 273-278. IEEE Computer Society, (2008)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)A Process Scheduler-Based Approach to NoC Power Management., , , , , , and . VLSI Design, page 77-82. IEEE Computer Society, (2007)Effect of Power Optimizations on Soft Error Rate., , , , and . VLSI-SoC (Selected Papers), volume 200 of IFIP, page 1-20. Springer, (2003)Split-Path Fused Floating Point Multiply Accumulate (FPMAC)., , , , , , , and . IEEE Symposium on Computer Arithmetic, page 17-24. IEEE Computer Society, (2013)A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS., , , , , , , , , and . ISSCC, page 328-329. IEEE, (2010)The Effect of Threshold Voltages on the Soft Error Rate., , , , and . ISQED, page 503-508. IEEE Computer Society, (2004)Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits., , , , , , , and . IEEE Trans. Dependable Secur. Comput., 6 (3): 202-216 (2009)