( en | de | ru )

 

Disambiguation of "Lee, Jae-Jin"

Author of the publication

copydeleteadd this publication to your clipboard
TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1758-1770 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jae Jin Kim

Jae Jin Myung

Seung-Jae Lee

Jae-Hoon Lee

Jae One Lee

 

Other publications of authors with the same name

Application specific processor for multi-standard video decoding., and . ISOCC, page 436-439. IEEE, (2011)New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding., , and . IEEE Trans. Circuits Syst. Video Techn., 20 (7): 1007-1017 (2010)Strategic Control of 60 GHz Millimeter-Wave High-Speed Wireless Links for Distributed Virtual Reality Platforms., , and . Mob. Inf. Syst., (2017)84% High efficiency dynamic voltage scaler with nano-second settling time based on charge-pump and BWC-DAC., , and . Microelectron. J., (2018)Flexible Multi-Core Platform for a Multiple-Format Video Decoder., , , , , and . J. Signal Process. Syst., 80 (2): 163-179 (2015)A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties., , , and . IEEE Des. Test, 36 (2): 81-87 (2019)A New Application-Specific PLD Architecture., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (6): 1425-1433 (2005)Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier., and . FPGA, page 249. ACM, (2004)Design of a Reversible PLD Architecture., , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 85-90. Springer, (2007)Efficient spiking neural network training and inference with reduced precision memory and computing., , , , , and . IET Comput. Digit. Tech., 13 (5): 397-404 (2019)