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A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties.

, , , and . IEEE Des. Test, 36 (2): 81-87 (2019)

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Application specific processor for multi-standard video decoding., and . ISOCC, page 436-439. IEEE, (2011)New Lookup Tables and Searching Algorithms for Fast H.264/AVC CAVLC Decoding., , and . IEEE Trans. Circuits Syst. Video Techn., 20 (7): 1007-1017 (2010)Flexible Multi-Core Platform for a Multiple-Format Video Decoder., , , , , and . J. Signal Process. Syst., 80 (2): 163-179 (2015)A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties., , , and . IEEE Des. Test, 36 (2): 81-87 (2019)84% High efficiency dynamic voltage scaler with nano-second settling time based on charge-pump and BWC-DAC., , and . Microelectron. J., (2018)A New Application-Specific PLD Architecture., and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (6): 1425-1433 (2005)Strategic Control of 60 GHz Millimeter-Wave High-Speed Wireless Links for Distributed Virtual Reality Platforms., , and . Mob. Inf. Syst., (2017)Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier., and . FPGA, page 249. ACM, (2004)User Recognition Based on Human Body Impulse Response: A Feasibility Study., , , , and . IEEE Access, (2020)Design of a Reversible PLD Architecture., , and . ARC, volume 4419 of Lecture Notes in Computer Science, page 85-90. Springer, (2007)