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Disambiguation of "Sarkar, Pallabi"

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Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis.

, , , and . CCECE, page 538-543. IEEE, (2011)

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Anindita Sarkar

Tapabrato Sarkar

Abhijit Sarkar

Abhishek Sarkar

Abhijit Sarkar

 

Other publications of authors with the same name

A Firefly Algorithm Driven Approach for High Level Synthesis., , , and . iNIS, page 15-19. IEEE, (2017)Designing Low-Cost Hardware Accelerators for CE Devices Hardware Matters., , , and . IEEE Consumer Electronics Magazine, 6 (4): 140-149 (2017)Integrated design space exploration based on power-performance trade-off using genetic algorithm., , and . ACAI, page 77-81. ACM, (2011)System Complexity Reduction Using 3-D Matrices and Novel Logic Gates., and . ICCCNT, page 1-5. IEEE, (2023)Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis., , , and . CCECE, page 538-543. IEEE, (2011)Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications., , , and . CCECE, page 533-537. IEEE, (2011)A multi parametric optimization based novel approach for an efficient design space exploration for ASIC design., , , , and . ICACCI, page 868-873. IEEE, (2013)Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis., , and . ACAI, page 82-85. ACM, (2011)GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis., , and . CCECE, page 75-80. IEEE, (2015)Signature-Free Watermark for Protecting Digital Signal Processing Cores Used in CE Devices Hardware Matters., , , and . IEEE Consumer Electronics Magazine, 8 (1): 92-94 (2019)