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Disambiguation of "Morishita, Fukashi"

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A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System.

, , , , , and . A-SSCC, page 1-3. IEEE, (2023)

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Kyoko Morishita

 

Other publications of authors with the same name

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 40 (1): 245-253 (2005)A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 40 (11): 2296-2304 (2005)A Low Noise 8Mpixel CMOS Image Sensor with 5.36GHz Global Counter and Dual Latch Skew Canceler for Surveillance AI Camera System., , , , , and . A-SSCC, page 1-3. IEEE, (2023)A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI., , , , , and . CICC, page 429-432. IEEE, (2006)A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 40 (1): 204-212 (2005)A Low Power Embedded DRAM Macro for Battery-Operated LSIs., , , , , , , , , and 2 other author(s). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2991-3000 (2003)A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems., , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit., , , , , , , and . VLSIC, page 1-2. IEEE, (2014)An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design., , , , , , , and . IEICE Trans. Electron., 89-C (11): 1519-1525 (2006)On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform., , , and . IEICE Trans. Electron., 92-C (3): 356-363 (2009)