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Disambiguation of "Hayashi, Isamu"

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A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications.

, , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 40 (1): 204-212 (2005)

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Ken Hayashi

Isamu Momozumi

Isamu Momozumi

Mutsumi Hayashi

Akiko Hayashi

 

Other publications of authors with the same name

0.5 V multi-phase digital controlled oscillator with smooth phase transition circuit., , , , and . APCCAS, page 232-235. IEEE, (2010)A 0.7V 4.1mW 850Mbps/ch inductive-coupling transceiver with adaptive pulse width controller in 65nm CMOS., , , , and . RWS, page 71-74. IEEE, (2012)A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (11): 2671-2680 (2013)A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI., , , , , , , , and . IEICE Trans. Electron., 90-C (4): 765-771 (2007)An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design., , , , , , , and . IEICE Trans. Electron., 89-C (11): 1519-1525 (2006)A 0.5V 6-bit scalable phase interpolator., , , , and . APCCAS, page 1019-1022. IEEE, (2010)A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture., , , , , , , , , and 7 other author(s). IEEE J. Solid State Circuits, 40 (1): 245-253 (2005)A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI., , , , , and . CICC, page 429-432. IEEE, (2006)A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 40 (1): 204-212 (2005)A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs., , , , , and . IEEE J. Solid State Circuits, 42 (11): 2611-2619 (2007)