Author of the publication

Specification and Formal Synthesis of Digital Circuits.

, , and . TPHOLs, volume A-20 of IFIP Transactions, page 475-484. North-Holland/Elsevier, (1992)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Quantitative Evaluation of Formal Based Synthesis in ASIC Design., , , , and . TPCD, volume 901 of Lecture Notes in Computer Science, page 286-291. Springer, (1994)Design-Flow and Synthesis for ASICs: A Case Study., , , , , and . DAC, page 292-297. ACM Press, (1995)A multi level testability assistant for VLSI design., , , , and . EURO-DAC, page 258-263. IEEE Computer Society Press, (1992)Property verification in the design of telecom applications., , and . ASP-DAC, page 167-172. IEEE, (1997)ALADIN: a multilevel testability analyzer for VLSI system design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 2 (2): 157-171 (1994)Specification and Formal Synthesis of Digital Circuits., , and . TPHOLs, volume A-20 of IFIP Transactions, page 475-484. North-Holland/Elsevier, (1992)IP-based design of custom field programmable network processors., , , , , and . ICECS, page 467-471. IEEE, (1998)A Design Methodology for the Exploitation of High Level Communication Synthesis., and . DATE, page 180-185. IEEE Computer Society, (2004)Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks., , , , , and . DFT, page 223-230. IEEE Computer Society, (1993)An Expert Solution to Functional Testability Analysis of VLSI Circuits., , , , , and . SEKE, page 263-265. Knowledge Systems Institute, (1993)