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Quantitative Evaluation of Formal Based Synthesis in ASIC Design., , , , and . TPCD, volume 901 of Lecture Notes in Computer Science, page 286-291. Springer, (1994)A multi level testability assistant for VLSI design., , , , and . EURO-DAC, page 258-263. IEEE Computer Society Press, (1992)Property verification in the design of telecom applications., , and . ASP-DAC, page 167-172. IEEE, (1997)Design-Flow and Synthesis for ASICs: A Case Study., , , , , and . DAC, page 292-297. ACM Press, (1995)The Patricia testability analysis tool., , , , , and . Microprocessing and Microprogramming, 32 (1-5): 675-682 (1991)Specification and Formal Synthesis of Digital Circuits., , and . TPHOLs, volume A-20 of IFIP Transactions, page 475-484. North-Holland/Elsevier, (1992)ALADIN: a multilevel testability analyzer for VLSI system design., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 2 (2): 157-171 (1994)A design methodology for the correct specification of VLSI systems., , , , , and . Microprocess. Microprogramming, 38 (1-5): 563-570 (1993)Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks., , , , , and . DFT, page 223-230. IEEE Computer Society, (1993)An Expert Solution to Functional Testability Analysis of VLSI Circuits., , , , , and . SEKE, page 263-265. Knowledge Systems Institute, (1993)