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Accelerating Fully Homomorphic Encryption over the Integers with Super-size Hardware Multiplier and Modular Reduction.

, , , , and . IACR Cryptology ePrint Archive, (2013)

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Novel lightweight FF-APUF design for FPGA., , , and . SoCC, page 75-80. IEEE, (2016)A Theoretical Model to Link Uniqueness and Min-Entropy for PUF Evaluations., , , , and . IEEE Trans. Computers, 68 (2): 287-293 (2019)Exploiting Collisions in Addition Chain-Based Exponentiation Algorithms Using a Single Trace., , and . CT-RSA, volume 9048 of Lecture Notes in Computer Science, page 431-448. Springer, (2015)Empirical evaluation of multi-device profiling side-channel attacks., , , and . SiPS, page 226-231. IEEE, (2014)Pre-processing power traces to defeat random clocking countermeasures., , and . ISCAS, page 85-88. IEEE, (2015)A Flip-Flop Based Arbiter Physical Unclonable Function (APUF) Design with High Entropy and Uniqueness for FPGA Implementation., , , , , and . IEEE Trans. Emerg. Top. Comput., 9 (4): 1853-1866 (2021)Stacked Ensemble Model for Enhancing the DL based SCA., , , , and . SECRYPT, page 59-68. SCITEPRESS, (2022)An Improved Second-Order Power Analysis Attack Based on a New Refined Expecter - - Case Study on Protected AES -., , , and . WISA, volume 9503 of Lecture Notes in Computer Science, page 174-186. Springer, (2015)FPGA-based strong PUF with increased uniqueness and entropy properties., , and . ISCAS, page 1-4. IEEE, (2017)A Hardware Wrapper for the SHA-3 Hash Algorithms., , , , , , and . IACR Cryptology ePrint Archive, (2010)