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Automated Modeling of Custom Digital Circuits for Test.

. DATE, page 954-961. IEEE Computer Society, (2002)

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Automated Modeling of Custom Digital Circuits for Test.. DATE, page 954-961. IEEE Computer Society, (2002)Path delay fault simulation of sequential circuits., , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 453-461 (1993)Concurrent Fault Simulation of Logic Gates and Memory Blocks on Message Passing Multicomputers., and . DAC, page 332-335. IEEE Computer Society Press, (1992)A rated-clock test method for path delay faults., , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (2): 323-331 (1998)Verifying pipelined hardware using symbolic logic simulation., and . ICCD, page 217-221. IEEE, (1989)Extraction of Schematic Array Models for Memory Circuits., and . DATE, page 570-577. IEEE Computer Society, (2004)Delay Test Quality Evaluation Using Bounded Gate Delays., and . VTS, page 23-28. IEEE Computer Society, (2007)The optimistic update theorem for path delay testing in sequential circuits., , and . J. Electron. Test., 4 (3): 285-290 (1993)Algorithms for Switch Level Delay Fault Simulation., , and . ITC, page 982-991. IEEE Computer Society, (1997)A Path Delay Fault Simulator for Sequential Circuits., , and . VLSI Design, page 269-274. IEEE Computer Society, (1993)