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A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies.

, , , , , , and . Microelectron. Reliab., 41 (3): 335-348 (2001)

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ESD: Design For IC Chip Quality and Reliability.. ISQED, page 251-. IEEE Computer Society, (2000)Latchup in voltage tolerant circuits: a new phenomenon., , , and . Microelectron. Reliab., 44 (4): 549-562 (2004)System efficient ESD design., and . Microelectron. Reliab., 55 (12): 2607-2613 (2015)ESD: a pervasive reliability concern for IC technologies., and . Proc. IEEE, 81 (5): 690-702 (1993)Thermal Failure Simulation for Electrical Overstress in Semiconductor Devices., , and . ISCAS, page 1389-1392. IEEE, (1993)Circuit design issues in multi-gate FET CMOS technologies., , , , , , , , , and 5 other author(s). ISSCC, page 1656-1665. IEEE, (2006)Circuit-level electrothermal simulation of electrical overstress failures in advanced MOS I/O protection devices., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (4): 482-493 (1994)Gate oxide failures due to anomalous stress from HBM ESD testers., , , , , , and . Microelectron. Reliab., 46 (5-6): 656-665 (2006)Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies., and . Microelectron. Reliab., 45 (9-11): 1406-1414 (2005)Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract).. ISQED, page 8. IEEE Computer Society, (2002)