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An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory.

, , , , , , , , , and . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)

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An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros., , , , , , and . IEEE J. Solid State Circuits, 50 (9): 2188-2198 (2015)An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory., , , , , , , , , and 3 other author(s). ISSCC, page 206-208. IEEE, (2011)A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time., , , , , , , , and . ISSCC, page 434-436. IEEE, (2012)A Process Variation Tolerant Embedded Split-Gate Flash Memory Using Pre-Stable Current Sensing Scheme., and . IEEE J. Solid State Circuits, 44 (3): 987-994 (2009)Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 50 (6): 1491-1501 (2015)A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (9): 2250-2259 (2013)