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Reducing instruction cache energy consumption using a compiler-based strategy., , , , , and . ACM Trans. Archit. Code Optim., 1 (1): 3-33 (2004)Compiler-directed instruction cache leakage optimization., , , , , and . MICRO, page 208-218. ACM/IEEE Computer Society, (2002)Compiler-Directed Code Restructuring for Operating with Compressed Arrays., , , , and . VLSI Design, page 221-226. IEEE Computer Society, (2007)A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks., , , , , , and . VLSI Design, page 657-664. IEEE Computer Society, (2006)Soft errors issues in low-power caches., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (10): 1157-1166 (2005)Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits., , , , , , , and . IEEE Trans. Dependable Secur. Comput., 6 (3): 202-216 (2009)Soft error and energy consumption interactions: a data cache perspective., , , , and . ISLPED, page 132-137. ACM, (2004)The Effect of Threshold Voltages on the Soft Error Rate., , , , and . ISQED, page 503-508. IEEE Computer Society, (2004)Analyzing Soft Errors in Leakage Optimized SRAM Design., , and . VLSI Design, page 227-233. IEEE Computer Society, (2003)Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings., , and . VLSI Design, page 227-232. IEEE Computer Society, (2007)