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Reducing instruction cache energy consumption using a compiler-based strategy.

, , , , , and . ACM Trans. Archit. Code Optim., 1 (1): 3-33 (2004)

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The Arithmetic Cube: error analysis and simulation., , and . ASAP, page 129-143. IEEE, (1991)Implementing a family of high performance, micrograined architectures., , , , and . ASAP, page 191-205. IEEE, (1992)Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories., , , , , and . ASP-DAC/VLSI Design, page 288-. IEEE Computer Society, (2002)Online Pipeline Systems for Recursive Numeric Computations., and . ISCA, page 292-299. ACM, (1980)On the Effects of Process Variation in Network-on-Chip Architectures., , , , , , and . IEEE Trans. Dependable Secur. Comput., 7 (3): 240-254 (2010)Managing Leakage Energy in Cache Hierarchies., , , , , , and . J. Instruction-Level Parallelism, (2003)The design and implementation of the Arithmetic Cube II, a VLSI signal processing system., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 491-502 (1993)The design of the MGAP-2: a micro-grained massively parallel array., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (6): 709-716 (2000)Design considerations for databus charge recovery., , , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (1): 104-106 (2001)A clock power model to evaluate impact of architectural and technology optimizations., , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (6): 844-855 (2002)