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Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.

C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popovic, H. Li, H. Smith, J. Hoyt, F. Kärtner, R. Ram, V. Stojanovic, and K. Asanovic. IEEE Micro, 29 (4): 8-21 (2009)

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FASED: FPGA-Accelerated Simulation and Evaluation of DRAM.D. Biancolin, S. Karandikar, D. Kim, J. Koenig, A. Waterman, J. Bachrach, and K. Asanovic. FPGA, page 330-339. ACM, (2019)An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.C. Schmidt, J. Wright, Z. Wang, E. Chang, A. Ou, W. Bae, S. Huang, V. Milovanovic, A. Flynn, B. Richards and 3 other author(s). IEEE J. Solid State Circuits, 57 (1): 140-152 (2022)Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology.J. Bilmes, K. Asanovic, C. Chin, and J. Demmel. International Conference on Supercomputing, page 340-347. ACM, (1997)Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors.R. Jevtic, H. Le, M. Blagojevic, S. Bailey, K. Asanovic, E. Alon, and B. Nikolic. IEEE Trans. Very Large Scale Integr. Syst., 23 (4): 723-730 (2015)Energy-aware lossless data compression.K. Barr, and K. Asanovic. ACM Trans. Comput. Syst., 24 (3): 250-291 (2006)The GAP Benchmark Suite.S. Beamer, K. Asanovic, and D. Patterson. CoRR, (2015)Building Open Trusted Execution Environments.D. Kohlbrenner, S. Shinde, D. Lee, K. Asanovic, and D. Song. IEEE Secur. Priv., 18 (5): 47-56 (2020)FPGA Accelerated INDEL Realignment in the Cloud.L. Wu, D. Bruns-Smith, F. Nothaft, Q. Huang, S. Karandikar, J. Le, A. Lin, H. Mao, B. Sweeney, K. Asanovic and 2 other author(s). HPCA, page 277-290. IEEE, (2019)Direction-optimizing breadth-first search.S. Beamer, K. Asanovic, and D. Patterson. SC, page 12. IEEE/ACM, (2012)FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.S. Karandikar, H. Mao, D. Kim, D. Biancolin, A. Amid, D. Lee, N. Pemberton, E. Amaro, C. Schmidt, A. Chopra and 6 other author(s). ISCA, page 29-42. IEEE Computer Society, (2018)

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Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.

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copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.

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Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.