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Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.

T. Onuki, W. Uesugi, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, J. Wu, C. Shuai, S. Wu, J. Myers, K. Doppler, M. Fujita, and S. Yamazaki. IEEE J. Solid State Circuits, 52 (4): 925-932 (2017)

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Chi-Yao Chang

Li-Chi Chang

Wenjing Shuai

Jianyun Shuai

Shuai Yuan

Other publications of authors with the same name

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme.M. Chang, C. Chen, T. Chang, C. Shuai, Y. Wang, Y. Chen, and H. Yamauchi. IEEE J. Solid State Circuits, 52 (9): 2498-2514 (2017)17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme.M. Chang, C. Chen, T. Chang, C. Shuai, Y. Wang, and H. Yamauchi. ISSCC, page 1-3. IEEE, (2015)Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS.T. Onuki, W. Uesugi, H. Tamura, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, C. Lin, J. Wu and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.T. Onuki, W. Uesugi, A. Isobe, Y. Ando, S. Okamoto, K. Kato, T. Yew, J. Wu, C. Shuai, S. Wu and 4 other author(s). IEEE J. Solid State Circuits, 52 (4): 925-932 (2017)

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Disambiguation of "Shuai, Chi Chang"

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Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.

Please choose a person to relate this publication to

Chi-Yao Chang

Li-Chi Chang

Wenjing Shuai

Jianyun Shuai

Shuai Yuan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Shuai, Chi Chang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.

Please choose a person to relate this publication to

Chi-Yao Chang

Li-Chi Chang

Wenjing Shuai

Jianyun Shuai

Shuai Yuan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS.