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A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs.

, , , , , , , , , , , , , и . IEEE J. Solid State Circuits, 48 (11): 2582-2594 (2013)

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Jafar Tabatabai

Jafar Mehrabani

Samir Jafar

Asadollah Jafarzadeh

Fariba Jafar-Shaghaghi

 

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2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS., , , , , , , и . ISSCC, стр. 52-53. IEEE, (2014)Session 21 overview: Analog techniques: Analog subcommittee., и . ISSCC, стр. 356-357. IEEE, (2012)High-speed transceivers: Standards, challenges, and future., , , , , и . ISSCC, стр. 522-523. IEEE, (2011)Clocking circuits for wireline communications., и . CICC, стр. 526-527. IEEE, (2005)Session 10 overview: Analog techniques., и . ISSCC, стр. 170-171. IEEE, (2013)F6: Mixed-signal/RF design and modeling in next-generation CMOS., , , и . ISSCC, стр. 510-511. IEEE, (2013)Technologies that could change the world - You decide!, и . ISSCC, стр. 515. IEEE, (2012)Time-Variant Characterization and Compensation of Wideband Circuits., , , и . CICC, стр. 487-490. IEEE, (2007)A Low-Power 0.5-6.6 Gb/s Wireline Transceiver Embedded in Low-Cost 28 nm FPGAs., , , , , , , , , и 4 other автор(ы). IEEE J. Solid State Circuits, 48 (11): 2582-2594 (2013)Wideband flexible-reach techniques for a 0.5-16.3Gb/s fully-adaptive transceiver in 20nm CMOS., , , , , , , , , и 3 other автор(ы). CICC, стр. 1-4. IEEE, (2014)