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Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits.

, , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)

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Power modeling and characterization of Graphene-based logic gates., , , and . PATMOS, page 223-226. IEEE, (2013)Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., , , , , and . DATE, page 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions., , , , and . ACM Great Lakes Symposium on VLSI, page 253-258. ACM, (2015)Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores., , , and . ICECS, page 598-601. IEEE, (2019)EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets., , and . AICAS, page 233-237. IEEE, (2020)NBTI-Aware Clustered Power Gating., , and . ACM Trans. Design Autom. Electr. Syst., 16 (1): 3 (2010)Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits., , , and . ISLPED, page 217-220. ACM, (2008)Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks., , , , , , , , and . DATE, page 165-166. IEEE, (2012)Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating., , , , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 214-225. Springer, (2011)Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks., and . DATE, page 114-119. IEEE, (2021)