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Disambiguation of "Calimera, Andrea"

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Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores.

, , , and . ICECS, page 598-601. IEEE, (2019)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)

Michaela Andrea Fingas

Resultate nach radikaler Prostatektomie bei Patienten mit einem Prostatakarzinom Gleason 7-10. Uni Marburg, (2009)

Andrea Krause

 

Other publications of authors with the same name

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., , , , , and . DATE, page 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions., , , , and . ACM Great Lakes Symposium on VLSI, page 253-258. ACM, (2015)Power modeling and characterization of Graphene-based logic gates., , , and . PATMOS, page 223-226. IEEE, (2013)Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores., , , and . ICECS, page 598-601. IEEE, (2019)EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets., , and . AICAS, page 233-237. IEEE, (2020)Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (3): 406-418 (2013)NBTI-Aware Clustered Power Gating., , and . ACM Trans. Design Autom. Electr. Syst., 16 (1): 3 (2010)Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits., , , and . ISLPED, page 217-220. ACM, (2008)Adaptive Test-Time Augmentation for Low-Power CPU., , , , and . CoRR, (2021)Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)