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High level energy modeling of controller logic in data caches.

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MDS and I-perfect poset block codes., , and . Finite Fields Their Appl., (2020)Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation, , and . CoRR, (2013)High level energy modeling of controller logic in data caches., , , , , , and . ACM Great Lakes Symposium on VLSI, page 45-50. ACM, (2014)The packing radius of a poset block code., , and . Discret. Math. Algorithms Appl., 7 (4): 1550045:1-1550045:10 (2015)Array scalarization in high level synthesis., , , , , and . ASP-DAC, page 622-627. IEEE, (2014)Energy efficient data flow transformation for Givens Rotation based QR Decomposition., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures., , , , and . ACM Trans. Embed. Comput. Syst., 15 (3): 59:1-59:23 (2016)Exploration of Loop Unroll Factors in High Level Synthesis., , , , and . VLSID, page 465-466. IEEE Computer Society, (2018)Array Interleaving - An Energy-Efficient Data Layout Transformation., , , , and . ACM Trans. Design Autom. Electr. Syst., 20 (3): 44:1-44:26 (2015)Energy optimization in Android applications through wakelock placement., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)