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Disambiguation of "Yoshimoto, Shusuke"

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An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology.

, , , , , , , , and . ICECS, page 532-535. IEEE, (2016)

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Kei Yoshimoto

 

Other publications of authors with the same name

A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM., , , , , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2016)Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector., , , , , , , , , and 4 other author(s). IEEE Trans. Biomed. Circuits Syst., 9 (5): 641-651 (2015)A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor., , , , , , and . IEICE Trans. Electron., 99-C (8): 901-908 (2016)Flexible electronics for bio-signal monitoring in implantable applications., , , , and . IEICE Electron. Express, 14 (20): 20172003 (2017)A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems., , , , , , , , , and 5 other author(s). BioCAS, page 280-283. IEEE, (2014)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)7T SRAM enabling low-energy simultaneous block copy., , , , , and . CICC, page 1-4. IEEE, (2010)A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme., , , , , , and . IEICE Trans. Electron., 95-C (4): 572-578 (2012)A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique., , , , , , and . IEICE Electron. Express, 9 (12): 1023-1029 (2012)