( en | de | ru )

 

Disambiguation of "Nakagawa, Tomoki"

Author of the publication

copydeleteadd this publication to your clipboard
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems.

, , , , , , , , , , , , , , and . BioCAS, page 280-283. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Koshiro Nakagawa

Julia Nakagawa

Tomoki Waragai

Yôichi Nakagawa

Kumiko Nakagawa

 

Other publications of authors with the same name

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology., , , , , , , , , and 42 other author(s). ISSCC, page 210-212. IEEE, (2019)A 6T-4C shadow memory using plate line and word line boosting., , , , , , and . ISCAS, page 2736-2739. IEEE, (2014)Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector., , , , , , , , , and 4 other author(s). IEEE Trans. Biomed. Circuits Syst., 9 (5): 641-651 (2015)A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems., , , , , , , , , and 5 other author(s). BioCAS, page 280-283. IEEE, (2014)A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology., , , , , , , , and . ICECS, page 532-535. IEEE, (2016)A Coupling-based Complexity Metric for Remote Component-based Software Systems Toward Maintainability Estimation., , , and . APSEC, page 79-86. IEEE Computer Society, (2006)A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology., , , , , , , , , and 39 other author(s). IEEE J. Solid State Circuits, 55 (1): 178-188 (2020)Sonic communication using multiple bands with electrostatic drivers., and . SII, page 973-974. IEEE, (2022)A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (4): 1442-1453 (2019)