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Accumulator-based generation for serial TPG., and . Panhellenic Conference on Informatics, page 426-430. ACM, (2015)SIC pair generation in near-optimal time with carry-look ahead adders., and . DTIS, page 1-2. IEEE, (2018)A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition., and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (10): 1041-1045 (2008)High performance MAC designs., , , and . IDT, page 30-35. IEEE, (2014)Test set embedding into accumulator-generated sequences targeting hard-to-detect faults., , , , , and . IDT, page 1-2. IEEE, (2013)Diminished-1 Modulo 2n + 1 Squarer Design., and . DSD, page 380-386. IEEE Computer Society, (2004)Low Cost Boolean Function generation., and . PCI, page 62. ACM, (2016)High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands., , and . IEEE Symposium on Computer Arithmetic, page 211-217. IEEE Computer Society, (2001)ALU based address generation for RAMs., , , and . DTIS, page 1-6. IEEE, (2012)Test set embedding into low-power sequences based on a traveling salesman problem formulation., , , and . DTIS, page 1-6. IEEE, (2012)