( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.

, , , , , , , , , , , , , , , , , и . CICC, стр. 45-49. IEEE, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Peter H Kunerth

Peter H Kornicker

H Peter Rodemann

Peter H Werhahn

H Peter Gieseler

 

Другие публикации лиц с тем же именем

Invited speakers II - Real-time supercomputing and technology for games and entertainment.. SC, стр. 199. ACM Press, (2006)Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow., , , , и . ARC, том 11444 из Lecture Notes in Computer Science, стр. 32-47. Springer, (2019)Distributing a Class of Sequential Programs.. MPC, том 669 из Lecture Notes in Computer Science, стр. 139-162. Springer, (1992)SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs., , , , , , , и . IPDPS, стр. 728-738. IEEE, (2022)Tydi-lang: A Language for Typed Streaming Hardware., , , , , , и . SC Workshops, стр. 520-529. ACM, (2023)High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor., , , , , , и . VTS, стр. 234-238. IEEE Computer Society, (1998)A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress., , , , и . CODES+ISSS, стр. 16. IEEE / ACM, (2018)Derivation of a rotator circuit with homogeneous interconnect., и . Inf. Process. Lett., 77 (2-4): 131-135 (2001)"Timing closure by design, " a high frequency microprocessor design methodology., , , , , , , , , и 7 other автор(ы). DAC, стр. 712-717. ACM, (2000)ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation., , , , , , и . MICRO, стр. 868-880. IEEE, (2020)