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Fault Modeling and Defect Level Projections in Digital ICs.

, , , and . EDAC-ETC-EUROASIC, page 436-442. IEEE Computer Society, (1994)

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On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits., , , and . DFT, page 263-270. IEEE Computer Society, (1994)Fault Modeling and Defect Level Projections in Digital ICs., , , and . EDAC-ETC-EUROASIC, page 436-442. IEEE Computer Society, (1994)A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits., , and . FPL, page 481-486. IEEE, (2005)Hardware/software specialization through aspects: The LARA approach., , , , , and . ICSAMOS, page 260-267. IEEE, (2012)DARP - A Digital Audio Reconfigurable Processor., , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 556-566. Springer, (2002)Physical DFT for High Coverage of Realistic Faults., , , , , , and . ITC, page 642-651. IEEE Computer Society, (1992)Realistic Fault Extraction for High-Quality Design and Test of VLSI Systems., , and . DFT, page 29-37. IEEE Computer Society, (1997)RTL design validation, DFT and test pattern generation for high defects coverage., , , and . ETW, page 99-105. IEEE Computer Society, (2001)Sampling Techniques of Non-Equally Probable Faults in VLSI System., and . VTS, page 283-288. IEEE Computer Society, (1998)Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems., , , and . IOLTS, page 164-165. IEEE Computer Society, (2003)