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GPU accelerated partial order multiple sequence alignment for long reads self-correction.

, , , , , , , and . IPDPS Workshops, page 174-182. IEEE, (2020)

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Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 14 (3): 15:1-15:33 (2021)Coordination of Independent Loops in Self-Adaptive Systems., , , , , and . ACM Trans. Reconfigurable Technol. Syst., 7 (2): 12:1-12:16 (2014)Floorplacement for Partial Reconfigurable FPGA-Based Systems., , , and . Int. J. Reconfigurable Comput., (2011)Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)., , , , , and . Int. J. Reconfigurable Comput., (2012)From reconfigurable architectures to self-adaptive autonomic systems.. Int. J. Embed. Syst., 4 (3/4): 172-181 (2010)On the automatic integration of hardware accelerators into FPGA-based embedded systems., , , , , and . FPL, page 607-610. IEEE, (2012)Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA., , , , , , and . ICSAMOS, page 107-114. IEEE, (2006)Towards a performance-as-a-service cloud., , , , , and . SoCC, page 26:1-26:2. ACM, (2013)Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices., , , , , and . ACM Great Lakes Symposium on VLSI, page 421-424. ACM, (2009)A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication., , , , and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 232-250. Springer, (2008)