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Disambiguation of "Mao, Zhigang"

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Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture.

, , , , , , and . DATE, page 1394-1399. IEEE, (2021)

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Zhigang Zhang

Zhigang Shen

Zhigang Zhang

Zhigang Zhang

Zhigang Gao

 

Other publications of authors with the same name

A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis., , and . ICECS, page 766-769. IEEE, (2008)Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code., , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (1): 127-135 (2014)Companding schemes based on transforming signal statistics into trigonal distributions for PAPR reduction in OFDM systems., , , , and . Int. J. Commun. Syst., 24 (6): 776-788 (2011)Near- and Sub-Vt Pipelines Based on Wide-Pulsed-Latch Design Techniques., , , , and . IEEE J. Solid State Circuits, 52 (9): 2475-2487 (2017)Synergistic Effect of BTI and Process Variations on Impact and Monitoring of Combination Circuit., , , , and . ASICON, page 1-4. IEEE, (2019)Pareto based Multi-objective Mapping IP Cores onto NoC Architectures., , and . APCCAS, page 331-334. IEEE, (2006)Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling., , , , , , and . IEEE Trans. Parallel Distributed Syst., 31 (9): 2201-2219 (2020)3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (1): 176-188 (January 2024)A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator., , , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (6): 57:1-57:22 (2022)A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations., , , , , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (2): 25:1-25:22 (2019)