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An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units.

Z. Li, F. Ge, F. Zhou, and N. Wu. ICCT, page 1521-1525. IEEE, (2022)

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Fen Wang

Fen Guo

Fen Zhou

Ge Yang

Junbo Ge

Other publications of authors with the same name

A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture.G. Feng, F. Ge, S. Yu, and N. Wu. ASICON, page 1-4. IEEE, (2013)Efficient Synchronization for Distributed Embedded Multiprocessors.H. Xiao, N. Wu, F. Ge, T. Isshiki, H. Kunieda, J. Xu, and Y. Wang. IEEE Trans. Very Large Scale Integr. Syst., 24 (2): 779-783 (2016)Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC.J. Zhan, J. Ouyang, F. Ge, J. Zhao, and Y. Xie. IEEE Trans. Very Large Scale Integr. Syst., 24 (10): 3041-3054 (2016)Distributed Synchronization for Message-Passing Based Embedded Multiprocessors.H. Xiao, N. Wu, F. Ge, G. Zhu, and L. Zhou. IEICE Trans. Inf. Syst., 98-D (2): 272-275 (2015)A network components insertion method for 3D application-specific Network-on-Chip.R. Zhou, F. Ge, G. Feng, and N. Wu. ASICON, page 1-4. IEEE, (2015)Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.F. Ge, J. Zhan, Y. Xie, and V. Narayanan. ISQED, page 565-570. IEEE, (2015)Collaborative thermal- and traffic-aware adaptive routing scheme for 3D network-on-chip systems.L. Shen, N. Wu, G. Yan, and F. Ge. IEICE Electron. Express, 18 (4): 20200425 (2021)RoR: A low insertion loss design of rearrangeable hybrid photonic-plasmonic 6 × 6 non-blocking router for ONoCs.M. Yahya, N. Wu, G. Yan, F. Ge, and T. Ahmed. IEICE Electron. Express, 16 (13): 20190346 (2019)Implementation of Bidirectional LSTM Accelerator Based on FPGA.H. Wang, D. Qiu, F. Ge, and Y. Yang. ICCT, page 1512-1516. IEEE, (2022)A Vehicle Line-Pressing Detection Approach Based on YOLOv5 and DeepSort.S. Wu, F. Ge, and Y. Zhang. ICCT, page 1745-1749. IEEE, (2022)

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Disambiguation of "Ge, Fen"

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An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units.

Please choose a person to relate this publication to

Fen Wang

Fen Guo

Fen Zhou

Ge Yang

Junbo Ge

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ge, Fen"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units.

Please choose a person to relate this publication to

Fen Wang

Fen Guo

Fen Zhou

Ge Yang

Junbo Ge

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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An A3C Deep Reinforcement Learning FPGA Accelerator based on Heterogeneous Compute Units.