( en | de | ru )

 

Disambiguation of "Verma, Ashutosh"

Author of the publication

copydeleteadd this publication to your clipboard
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.

, , and . Asian Test Symposium, page 107-112. IEEE Computer Society, (1999)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ashutosh Banerjee

Ashutosh Trivedi

Ashutosh Malaviya

Ashutosh Modi

Damian Verma

 

Other publications of authors with the same name

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 54 (5): 1254-1265 (2019)A 10b 500MHz 55mW CMOS ADC., and . ISSCC, page 84-85. IEEE, (2009)A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 57 (5): 1257-1266 (2022)Clustering Indian districts based on multidimensional demographic and climate data., , , , and . BuildSys@SenSys, page 450-455. ACM, (2022)A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW., , , , , , , , , and 16 other author(s). ISSCC, page 1-3. IEEE, (2022)Performance Analysis of Decode-and-Forward based Hybrid RF/FSO-VLC system., , and . ANTS, page 1-5. IEEE, (2019)A 10-Bit 500-MS/s 55-mW CMOS ADC., and . IEEE J. Solid State Circuits, 44 (11): 3039-3050 (2009)Snowpack Density Retrieval Using Fully Polarimetric TerraSAR-X Data in the Himalayas., , , , , , and . IEEE Trans. Geosci. Remote. Sens., 55 (11): 6320-6329 (2017)Frequency-Based Measurement of Mismatches Between Small Capacitors., and . CICC, page 481-484. IEEE, (2006)Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems., , and . VLSI Design, page 462-467. IEEE Computer Society, (2000)